1. Field of the Invention
The invention relates to digital circuits, and more particularly, to a method and apparatus for determining the timing specification for a digital integrated circuit.
2. Art Background
Digital circuits are rapidly increasing in complexity. Very Large Scale Integration ("VLSI") integrated circuits may contain thousands of circuit elements and a correspondingly large number of circuit connections. Despite this complexity, integrated circuit manufacturers must determine the specifications of their integrated circuits because the integrated circuits interact with other elements in a digital system. For example, a central processing unit (CPU) may interact with a random access memory (RAM) and a computer manufacturer must have accurate timing specifications for both. The complexity of modern digital circuits renders the determination of integrated circuit specifications a time consuming and difficult process.
Prior art techniques to determine the timing specification of a integrated circuit require a relatively large number of man hours. For example, a person using a static path tracing tool must manually trace and evaluate each path in a digital circuit, where a single path is defined as the circuit elements that process a particular input at an input pin to generate an output at an output pin. Further, subsidiary paths, such as a path from an input pin to a flip flop data input, must also be analyzed. Since the number of total paths on modern digital circuits is extremely large, determining a integrated circuit specification with a static path tracing tool requires a relatively large amount of time.
More specifically, with regard to synchronous circuits, "setup" and "hold" times must be specified for a integrated circuit. In synchronous circuits, the circuit elements are coupled to a digital clock input that controls the timing of data operations. There is a delay from the clock input to a particular circuit element and circuit elements in synchronous circuits will not process data until they receive the clock pulse. Most circuit elements require a data input a finite amount of time before receiving a clock pulse. This amount of time is typically referred to as the "setup" time. Also, most circuit elements require the data to be maintained for a certain amount of time after the clock input changes from a low value to a high value. This amount of time is known as the "hold" time.
The circuit must ensure that the setup and hold times for each data element are satisfied. To ensure that the setup and hold times for each element are satisfied, the data input and the clock input must be maintained at a certain element for the proper length of time. The required length of time that a data or clock value must be maintained depends upon the lag between the clock and data input to a certain element and the required setup and hold times for that particular element. According to the prior art, the required maintenance time for data and clock inputs to a integrated circuit is determined manually. As previously described, this is a time consuming process, particularly for large and complex integrated circuits.
The method and apparatus of the present invention overcomes the limitations of the prior art, and automatically determines the setup and hold times for a integrated circuit based upon user specified parameters of a circuit.